1. Field of the Invention
The present invention relates in general to a sense amplifier used in a semiconductor memory device such as a dynamic random access memory (DRAM), and more particularly to a sense amplifier which is capable of minimizing a data sensing time.
2. Description of the Prior Art
A conventional DRAM device has memory cells integrated therein, each of which is comprised of a transistor and a capacitor. The DRAM device is highly integrated to enhance a data storage capacity. However, the high integration of the DRAM device reduces a using voltage and limits a capacitance of the memory cell, thereby causing data to be read from the memory cell under the influence of a considerable noise. The reason is that a charge amount transferred from the memory cell to a bit line is reduced contrary to an integration degree of the DRAM device in reading the data.
Also, the highly integrated DRAM device comprises a sense amplifier for sensing and amplifying accurately and rapidly data of a low voltage on the bit line to enhance a data access speed. The sense amplifier is conventionally of the complementary metal oxide semiconductor (CMOS) latch type as shown in FIG. 1, which possesses a relatively small area and has a relatively stable operation. However, the sense amplifier of the CMOS latch type has a disadvantage in that it requires a long time to sense data on a bit line with a large capacitance because it is connected directly to the bit line. The long sensing time of the sense amplifier of the CMOS latch type causes the data access speed of the DRAM device not to be enhanced beyond a limited speed.
Referring to FIG. 1, the conventional sense amplifier of the CMOS latch type is shown to comprise two PMOS transistors P11 and P12. The PMOS transistors P11 and P12 have sources connected in common to a terminal for inputting a first sense amplifier control signal SAP having a power source voltage Vcc. The PMOS transistor P12 has a gate connected to a true bit line BL and the PMOS transistor P11 has a gate connected to a complementary bit line /BL. The PMOS transistor P11 has a drain connected to the true bit line BL and the PMOS transistor P12 has a drain connected to the complementary bit line /BL. The first PMOS transistor P11 inputs complementary data from a memory cell (not shown) through the complementary bit line /BL at its gate. If the inputted complementary data is "0", the first PMOS transistor P11 transfers the first sense amplifier control signal SAP to the true bit line BL. In this case, true data of "1" on the true bit line BL is amplified to have a voltage value of the first sense amplifier control signal SAP. On the contrary, when true data "0" from the memory cell is applied to the true bit line BL, the second PMOS transistor P12 transfers the first sense amplifier control signal SAP to the complementary bit line /BL. In this case, complementary data of "1" on the complementary bit line /BL is amplified to have the voltage value of the first sense amplifier control signal SAP.
The conventional sense amplifier of the CMOS latch type also comprises two NMOS transistors N11 and N12 connected to form a latch structure between the true and complementary bit lines BL and /BL. The NMOS transistors N11 and N12 have sources connected in common to a terminal for inputting a second sense amplifier control signal /SAN having a ground voltage GND. The NMOS transistor N12 has a gate connected to the true bit line BL and the NMOS transistor N11 has a gate connected to the complementary bit line /BL. The NMOS transistor N11 has a drain connected to the true bit line BL and the NMOS transistor N12 has a drain connected to the complementary bit line /BL. The true and complementary bit lines BL and /BL are connected to true and complementary data bus lines DB and /DB, respectively. The first NMOS transistor N11 inputs complementary data from the memory cell through the complementary bit line /BL at its gate. If the inputted complementary data is "1", the first NMOS transistor N11 transfers the second sense amplifier control signal /SAN to the true bit line BL. In this case, true data of "0" on the true bit line BL is attenuated to have a voltage value of the second sense amplifier control signal /SAN. On the contrary, when true data "1" from the memory cell is supplied to the true bit line BL, the second NMOS transistor N12 transfers the second sense amplifier control signal /SAN to the complementary bit line /BL. In this case, complementary data of "0" on the complementary bit line /BL is attenuated to have the voltage value of the second sense amplifier control signal /SAN. The PMOS and NMOS transistor pairs constituting the sense amplifier of the CMOS latch type are adapted to amplify the true and complementary data on the true and complementary bit lines BL and /BL to make a voltage difference therebetween large.
As mentioned above, the sense amplifier of the CMOS latch type shown in FIG. 1 possesses the relatively small area and has the relatively stable operation due to the small number of circuit elements. However, the sense amplifier of the CMOS latch type has the disadvantage that it requires much time to sense and amplify the data on the bit line with the large capacitance because it is connected directly to the bit line. For this reason, the sense amplifier of the CMOS latch type limits the data access speed of the DRAM device.